Random Number Generator Schematic
The circuit shown in the figure uses a standard white-noise maker using Q1, Q2, and R1. The noise is amplified by C1, R2, R3, and Q3, providing 1 or 2 V of noise at roughly 1 MHz. This circuit portion won't be reliably noisy when operated at less than 12 V. Final amplification is done with inverting gates. Any 74HC inverting gates will do, as would a single noninverting gate. However, the second gate filters out some partial transitions of the first.
R4â€”C3 has a very long time constant (>1000X) compared to noise frequency. If the cumulative gate-output duty cycle is 50% and swings rail-to-rail, the A1 voltage follower will output VCC/2, because C3 will charge and discharge to this average voltage. This same VCC/2 is created with R6 and R7. Both nodes are inputs to the A2 integrator, which has a long RC timing relative to the noise. The integrator is the voltage source for amplifier Q3; R3's value is chosen for the integrator to output a midrange 6.5 V. Now the feedback loop is complete: The integrator output will "find" the gate threshold, lock in a 50-50 balance of high and low logic timing, and compensate for variables like supply voltage, temperature, and IC variations.
This particular application, in a nightclub light sequencer, required only a byte of data at a slow rate. Further testing was done by displaying six of the 74HC164 outputs as a pair of octal digits and analyzing sets of many readings for bit content as shown in Table 1, available in the online version of this article. The circuit was chilled or heated to cause a 10% compensating shift in the integrator output. All digits 00 to 77 were well represented in each data set. If the application's 50-50 split is crucial, a more precise op amp or a different value of R6 can be used.
Return to the Schematic Archive